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TB62718AFG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62718AFG
Controller and Driver for Full-color LED Modules and Panels
The TB62718AFG is an LED driver which is suitable for driving full-color LED modules. This device has built-in 8 bit PWM grayscale and an output current adjustment functions. It can turn on to 16 LEDs. This device has a heat sink fitting side on the surface of the package. Then, a heat sink will dissipate heat generated in the device. In addition, this device incorporates built-in TSD (thermal Shutdown) and output-open detection functions to protect the device.
Features
* * * * Output current capability and number of outputs: 90 mA x 16 outputs Constant current range: 5 mA~75 mA Application output voltage: 0.7 V (output current 5 mA~90 mA) Adjustment function 1. Standard current adjustment (8-bit serial data input) This function supports standard current adjustment using an external resistance connected to the REXT pin. 2 high-order bits ... Output current can be adjusted to any one of 4 levels in the range 25%~100%. 6 low-order bits ... Output current can be adjusted to any one of 64 levels in the range 40%~100%. 2. Each dot adjustment (128-bit serial data input) This function allows adjustment of the current value for each output (dot). ... Output current can be adjusted to any one of 64 levels in the range 20%~100%. 3. All dot adjustment 1 (8-bit parallel data input) This function allows adjustment of brightness for each LED module. 5 low-order bits ... Output current can be adjusted to any one of 32 levels in the range 50%~100%. 4. All dot adjustment 2 (8-bit parallel data input) This function allows changes to the frequency of the PWM clock and allows major brightness adjustment for the display. 3 high-order bits ... PWM clock frequency can be adjusted to any one of 8 levels in the range 1/1~1/8. 5. 256-grayscale PWM function (8-bit parallel input) This function controls the pulse width for each output, yielding 256 grayscales. Maximum PWM clock frequency 10 MHz (for all temperature range), Minimum pulse width 2 ms * Accuracy of bits in constant-current output levels prior to adjustment 6.0% max (for output current of 40 mA~80 mA) 7.0% max (for output current of 20 mA~40 mA) 12.0% max (for output current of 5 mA~20 mA) * Protection functions 1. Thermal shutdown function (TSD) This function monitors the rise in junction temperature. Connect a pull-up resistor to the ALARM1 pin in order to monitor the temperature. 2. Output Pin Open Detection function This function detect when an output pin is open. Connect a pull-up resistor to the ALARM2 pin in order to monitor this.
Company Headquarters 3 Northway Lane North Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 California Sales Office: 950 South Coast Drive, Suite 265 Costa Mesa, California 92626 Toll Free: 800.984.5337 Fax: 714.850.9314
Weight: 0.26 g (typ.)
Web: www.marktechopto.com | Email: info@marktechopto.com
TB62718AFG
* * * * * * * For anode-common LEDs Input signal voltage level: CMOS level (Schmitt trigger input) Power supply voltage range VDD = 4.5 V~5.5 V Maximum output pin voltage: 26 V Serial and parallel data transfer rate: 20 MHz (max, cascade connection) Operating temperature range Topr = -40C~85C Package: HQFP64-P-1010-0.50. A Heat sink can be fitted.
Warnings
Short-circuiting an output pin to GND or to the power supply pin may destroy the device. Take care when wiring the output pins, the power supply pin and the GND pins (VSS, VSS2). Do not apply either positive or negative voltages to the heat sink on the surface of the IC. In addition, do not solder anything to the heat sink.
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Pin Assignment (top view) and Markings
Package type: HQFP64-P-1010-0.50
PI DATA 01 PI DATA 02 PI DATA 03 PI DATA 04 PI DATA 05 PI DATA 06 PI DATA 07 PI DATA 08 PI LATCH
48 DOE SI DATA SI CLK SI LATCH SI SEL PWMCLK BCEN DCEN
RESET
49
OUT 00 33 32
PI CLK
PI SEL
VSS2
VDD
VSS
NC
TB62718AFG
OUT 01 OUT 02 OUT 03 OUT 04 OUT 05 OUT 06 OUT 07 VSS2 VSS2 OUT 08 OUT 09 OUT 10 OUT 11 OUT 12 OUT 13
LED TEST BLANK REXT VSS SO DATA TSENA TEST0 64 1 PO DATA 04 PO DATA 05 PO DATA 06 PO DATA 00 PO DATA 01 PO DATA 02 PO DATA 03 PO DATA 07 TEST1 ALARM1 ALARM2 VDD NC VSS2 VSS
5WWKA**
16 OUT 15
17
OUT 14
Note:
Indicates device name on the upper surface of the package. Indicates weekly code on the lower surface of the package.
Details of weekly code on lower surface: From left, 1st character = rightmost digit of year 0 for 2000, 1 for 2001 2nd and 3rd characters = week of manufacture during year: maximum value = 52. 4th characters = manufacturing factory (`K' means the Kita Kyushu factory.) 5th to 7th characters = lot number within week 1st lot is A11, 2nd lot is A1 and 3rd lot is A. 4th lot is B11, 5th lot is B1 and 6th lot is B. 64th lot is Z11, 65th lot is Z1 and 66th lot is Z. The four characters of `I', `M', `O' and `W' are not used.
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Block Diagram (entire device)
PI DATA 00 ~PI DATA 07 PWMCLK SI SEL SI DATA 8
PI SEL
8 SI REG2 PI REG1 Each dot 8 8-bit clock counter register & latch (1 x 128 bits) adjustment data current adjustment data register & latch (1 x 8 bits) Standard All dot adjustment data register & latch (1 x 8 bits) 8 & latch (16 x 8 bits) data register PWM PI REG2 SI REG1
8
3
3-bit Clock counter SI CLK
PI CLK
BCEN
PI LATCH 8 PWM pulse 5 generator circuit (8 bits) 8
DCEN
SI LATCH
SO DATA 128
8
8 16 16 x 6 bit DACs and 16 constant-current outputs DAC4 DAC3 V/I conversion circuit 1 x 5-bit DAC
DOE PO DATA 00 ~PO DATA 07 OUT 00~OUT 15
DAC1 1 x 2-bit DAC
BLANK LED TEST Output-open detection circuit
ALARM2 TSD2 circuit TSD1 circuit
DAC2 1 x 6-bit DAC REXT For PI REG1, PI REG2, SI REG1 and SI REG2
RESET
ALARM1
TSENA
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Constant Current Adjustment Range (graph)
This graph shows how current may be adjusted to a fraction of its full-scale value.
Note 1: In each case, the value input to each DAC is the value output from the previous DAC. Reference: Current adjustment functions DAC1 to DAC3 are the current adjustment functions for all outputs. The adjustment width of DAC1 is large and approximate (1 LSB 25%). - The adjustment width of DAC2 is the smallest and has a large error (1 LSB 0.9%). - The adjustment width of DAC3 is small. DAC3 is a high-performance DAC with a small error (1 LSB 1.61%). - Therefore, It is recommended that DAC1 and DAC2 be used for adjusting the REXT resistance. It is recommended that DAC3 be used for adjusting brightness between module. (after it was set and it had DAC4 adjusted to the dot.) The beginning is set in about 75% of the middle value, after that, it is effective to use 25% of set width. DAC4 is the current adjustment function for all outputs. The adjustment width of DAC4 is small. But it is a high-performance DAC with a small error (1 LSB 1.27%). - And also, DAC4 has a very wide setting range. Therefore, DAC4 can be used to adjust the brightness of LEDs without a rank classification. This method allows brightness to be adjusted with a degree of accuracy of 1.27% of full scale. Note 2: Assuming precise linear correlation between output current and LED brightness
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Equivalent Input and Output Circuits (resistance values are typical values.)
Input pins with pull-up resistor
TSENA, BLANK, BC/DCEN
Input pins with pull-down resistor.
SI/PI LATCH, PI DATA 00~PI DATA 07, LED TEST
VDD
R (UP) = 300 k
VDD 1 k
IN
IN 1 k GND
GND
R (DOWN) = 300 k
Input terminals
(A) SI DATA, SI CLK, PI CLK, PWMCLK (B) RESET , DOE , PI SEL, SI SEL
Output terminals
PO DATA 00~PO DATA 07, SO DATA
VDD
VDD
IN
Rin
100 GND
OUT
GND
(A) Rin = 250 (B) Rin = 1 k
Protection circuit monitor terminals
ALARM1 & ALARM2 Parasitic diode VSS
Constant-current output terminals
OUT 00~OUT 15 Parasitic diode VSS2
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Explanation of Pin Functions Table
No. 4, 45 35, 14 63 15, 24, 25, 34 13, 36 16~23, 26~33 50 51 52 53 62 37~44 46 47 48 5~12 49 59 54 55 56 57 58 60 2
3 1, 64
Name VSS NC TSENA
I/O P

Function Explanation Logic ground pins. Be sure to use all. Unused This pin is used to reset the IC's built-in temperature monitoring circuit (TSD). Rising edge of input signal re-enables outputs which had been forced to OFF. The latched data as the setting is not reset. Either in case of H- or L-level of this terminals can be operated TSD circuit. Ground pin for output. Be sure to use all. Logic power supply input pins. Be sure to use all. LED drive output pins. Connect to cathode of LED. Serial data input pin. Used for input of standard current adjustment data and dot adjustment data Serial data transfer clock input pin. Data is transferred positive edge.
I
Pullup

VSS2 VDD OUT 00~ OUT 15 SI DATA SI CLK SI LATCH SI SEL SO DATA PI DATA 00~ PI DATA 07 PI CLK PI LATCH PI SEL PO DATA 00~ PO DATA 07 DOE BLANK PWMCLK BCEN DCEN
P P O I I I I O I I I I O I I I I I I I P O
O I
PullSerial data latch signal input pin. Data is held on positive edge. down

Serial data selection pin. Either standard current adjustment data or dot adjustment data may be selected. Serial data output pin. The output data type is selected using SI SEL.
PullInput pins for parallel data. Inputs for all output adjustment data and PWM data down
Input pin for parallel data transfer clock. Data is transferred on positive edge.
PullInput pin for parallel data latch signal. Data is held on rising positive edge. down

Parallel data selection pin. Either all output adjustment data or PWM data may be selected. Output pin for parallel data. The output data type is selected using PISEL. Control pin for parallel data output PODATA. PIDATA is out on input of an H-level signal. PIDATA is set to High-impedance by input of an L-level signal. PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM output is initiated by input of an L-level signal accordingly to the input data. Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum pulse width of the PWM output. Selection signal input pin for all output adjustment functions. All output adjustment is fixed to 100% when this signal is Low. All bit adjustments become effective when it is High. It isn't influent anything to all output adjustment by PWMCLK. Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to 100% when this signal is Low. Dot adjustment becomes effective when it is High. Reset signal input pin. Setting and registered data are reset when it is Low. A reset also releases TSD.
Pullup
Pullup Pullup
RESET
LED TEST REXT ALARM1
ALARM2 TEST 0, TEST 1
Connection confirmation signal input pin for an LED. When this signal is High, all outputs Pullare ON. down This signal should normally be kept Low.

Connection pin of resistor for setting for the current. Open-drain monitor pin for TSD circuit. When the TSD circuit detects an abnormal temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a pull-up resistor. ALARM1 is independent of the RESET signal.
Open-drain monitor pin for output-open detection circuit. When an open output is detected, this signal is turned ON. Pins for the device testing. Connect all these pins to ground.
Pin attributes
P: power supply/ground/other, I: input pin, O: output pin
Note 3: It is recommended that pins with pull-up or pull-down resistors not be left open. Ambient noise may cause malfunction of the device.
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Absolute Maximum Ratings (Topr = 25C unless otherwise specified)
Characteristics Supply voltage Constant-current output voltage Output current Logic output voltage Logic input voltage Total VSS2 current Power dissipation Saturation heat resistance of package When device mounted on PCB (Note 5) (Note 6) Symbol VDD VO IOUT VOUT VIN IVSS2 Pd (Note 4)
(j-a) (j-c)
Rating
-0.3~7 -0.3~26
Unit V V mA/bit V V A W
90
-0.3~ VDD + 0.3 -0.3~VDD + 0.3
1.44 1.19 5.0 102 25
-40~85 -55~150
When device mounted on PCB of any size When device mounted on PCB (Note 6)
When device mounted on PCB of any size
C/W C C
Operating temperature Storage temperature
Topr Tstg
Note 4: If the operating temperature exceeds 25C, derate the power dissipation rating by 0.95 mW/C. Note 5: All four VSS2 pins must be connected. If not, device characteristics cannot be guaranteed. Note 6: When device mounted on PCB with dimensions 100 mm x 100 mm x 1.6 mm
Recommended Operating Conditions
Characteristics Supply voltage High-level input voltage Symbol VDD VIH VIL IOH IOL IOUT VOUT VOH Topr
(VDD = 4.5 V~5.5 V, Topr = -40C~85C unless otherwise specified)
Conditions & Pins
Min 4.5 0.7 VDD VSS

Typ. 5.0

Max 5.5 VDD 0.3 VDD
-1
Unit V V
PI DATA, PI CLK, PI SEL, PI LATCH, SI DATA, SI CLK, SI SEL, SI LATCH, PWM CLK BLANK, LED TEST, TSENA, DOE, DCEN, BCEN PO DATA 00~PO DATA 07, SO DATA VDD = 4.5 V, ALARM1, ALARM2 OUT 00~OUT 15 OUT 00~OUT 15 OFF ALARM1, ALARM2 OFF
Low-level input voltage High-level output current Low-level output current Constant-current output Output voltage Operating temperature
V mA mA mA/bit V V C
1 80 26 5 85
5
-40
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Recommended Operating Conditions (continue)
Characteristics Symbol fPWM fPI1 Clock frequency fPI2 fSI1 fSI2 twH/twL twltH/twltL twrstH/twrstL twblkH/twblkL twledH/twledL
(VDD = 4.5 V~5.5 V, Topr = -40C~85C unless otherwise specified)
Condition & Terminals Ratio of High-level: Low level = 50%, PWM CLK PI CLK, PI CLK, connected in cascade SI CLK SI CLK, connected in cascade PWM CLK PI CLK, SI CLK PI LATCH, SI LATCH Min

Typ.

Max 10 15 10 15 10

Unit
MHz
30 30 50 50 400 400 10 10 10 10 50 5 5 5 5 50
Minimum pulse width
RESET
BLANK LED TEST PI DATA PI CLK PI LATCH PI CLK
ns
Set-up time
tsetup
SI DATA SI CLK SI LATCH SI CLK SI LATCH SI CEL PI DATA PI CLK PI LATCH PI CLK
ns
Hold time
thold
SI DATA SI CLK SI LATCH SI CLK SI LATCH SI CEL
ns
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Electrical Characteristics 1
Parameter High-level output voltage
(VDD = 4.5 V~5.5 V, Topr = -40C~85C, typ: VDD = 5.0 V, Topr = 25C)
Symbol VOH VOL IOZ II Test conditions & Terminals IOH = -1.0 mA, PO DATA 00~PO DATA 07, SO DATA IOL = 1.0 mA, PO DATA 00~PO DATA 07, SO DATA IOL = 1.0 mA, ALARM1, ALARM2 Tri-state output leakage current Input current VOUT = VDD or VSS, PO DATA 00~PO DATA 07 All pins without pull-up/pull-down resistors PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = 20 MHz PWMCLK = L, BLANK = H Settings: *1 PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *5a PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *5a PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *6a PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *6a Min VDD -0.4

Typ.
0.5
Max
Unit V
Low-level output voltage
0.4 0.3
5 1
V
A A
IDD1
20
30
IDD2
75
105
Supply current
IDD3
80
115
mA
IDD4
90
140
IDD5
95
150
Electrical Characteristic Settings
(OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 k unless otherwise specified)
No.
1 2 3a 4a 5a 6a 7 3b 4b 5b 6b
DAC Settings Outputs all OFF, VOUT = 26 V, DAC1, 2, 4 = MSB, BLANK = H DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L
Surface Brightness Adjustment (DAC3)
Constant Output Current (typ.) IOUT = 0 mA IOUT = 7.10 mA IOUT = 10.0 mA
DAC3 = 31
IOUT = 19.9 mA IOUT = 40.1 mA IOUT = 60.2 mA IOUT = 71.0 mA IOUT = 5.0 mA IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA
DAC3 = 00
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Electrical Characteristics 2
Parameter
(VDD = 4.5 V~5.5 V, Topr = -40C~85C, typ: VDD = 5.0 V, Topr = 25C)
Symbol IOUT1 IOUT2 Constant-current output IOUT3 IOUT4 IOUT5 IOUT6 Constant-current output Depends on temperature Leakage current for constant-current output %TOPR1 %TOPR2 IOLK
IOUT1
Test Conditions Settings *7 Settings *6a Settings *5a Settings *4a Settings *3a Settings *2 Settings *6a, VOUT = 1.0 V, Topr is varied in the range -40C~85C. Settings *4a, VOUT = 1.0 V, Topr is varied in the range -40C~85C. Settings *1, VOUT = 26 V Settings *6a, VOUT = 0.7 V Settings *5a, VOUT = 0.7 V Settings *4a, VOUT = 0.7 V Settings *3a, VOUT = 0.7 V Settings is changed from *6a to *6b. Settings is changed from *5a to *5b. Settings is changed from *4a to *4b. Settings is changed from *3a to *3b. Settings *6a, VOUT is varied in the range 0.7 V~3 V. Settings *4a, VOUT is varied in the range 0.7 V~3 V. Settings *6a, VDD is varied in the range 4.5 V~5.5 V.

Min 60.4 51.2 34.1 16.5 7.8 4.54

Typ. 71.0 60.2 40.1 19.9 10.0 7.1
50 25
Max 81.6 69.2 46.1 23.2 12.2 9.65
80
Unit
V
A/C 50
0.05
2.5 3.5 5.5 7 1 1.5 3.5 6 5 3 1
0.1
6 6 7 12 3 3 5 12 8
A
Constant current accuracy between bits
IOUT2 IOUT3 IOUT4
%
Dot adjustment deviation between bits (when DAC3 data were changed from MSB to LSB.)
%IOUT1 %IOUT2 %IOUT3 %IOUT4
%
Constant-current output depends on output voltage Constant-current output depends on supply voltage TSD detection temperature Output-open detection voltage Pull-up/down resistor
%VOUT
%
6 2
%VDD Tsd1 Tsd2 VARL Rup/Rdw
% C V k
120 140
140 160 0.04 VDD 300
160 180
ALARM2
150
600
Electrical Characteristic Settings
(OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 k unless otherwise specified)
No.
1 2 3a 4a 5a 6a 7 3b 4b 5b 6b
DAC Settings OUT00~15 OFF, VOUT = 26 V, DAC1~4 = MSB, BLANK = H DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L
All Dot Adjustment (DAC3)
Constant Output Current (typ.) IOUT = 0 mA IOUT = 7.10 mA IOUT = 10.0 mA
DAC3 = 31
IOUT = 19.9 mA IOUT = 40.1 mA IOUT = 60.2 mA IOUT = 71.0 mA IOUT = 5.0 mA IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA
DAC3 = 00
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Switching Characteristics
(VDD = 4.5 V~5.5 V, Topr = -40C~85C, CL = 50 pF unless otherwise specified,
typ: VDD = 5.0 V, Topr = 25C, CL = 50 pF)
Parameter Tri-state output enable propagation delay Tri-state output disable propagation delay Rise time Symbol tpZH/ZL tpHZ/LZ tr
Test Conditions DOE PO DATA0~ PO DATA 7 DOE PO DATA0~ PO DATA 7 OUT00~ OUT 15 ALARM1, ALARM2 OUT00~ OUT 15 ALARM1, ALARM2 BLANK OUT00~ OUT 15 PWM CLK OUT00~ OUT 15 PWM CLK OUT00~ OUT 15 LED TEST OUT00~ OUT 15 RESET OUT00~ OUT 15 PI CLK PO DATA0~ PO DATA 7
Min 8 8 10 0.2 20 2 30 70 40 60 30 30 20 20 10 10
Typ. 16 16 17 0.4 40 4 60 120 70 110 60 60 30 30 18 20
Max 30 30 30 0.8 70 8 120 200 140 190 130 130 70 70 40 40
Unit ns ns
s
ns ns
Fall time
tf tpHL tpLH tpHL tpLH
Propagation delay
tpHL tpHL
ns
tpd
PI SEL PO DATA0~ PO DATA 7 SI SEL SO DATA SI SEL SO DATA
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Explanation of Operation and Truth Tables
Serial data transfer: standard current adjustment using DAC1 and DAC2 (data register SI REG [7:0])
Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function Selects standard current adjustment (8 bits, 2 bits and 6 bits) for input data when SI SEL is high. Data is transferred to SI REG [1] on 8th positive edge of SI CLK input. Holds the data transferred to SI REG [1] on positive edge of SI LATCH. Set is reflected on standard current adjustment from the moment when it is held.
1 H or L 2 (x8)
L
H
H or L
L (x1)
H
No change
Serial data transfer timing (standard current adjustment, SI SEL = H, single device)
RESET
SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L SODATA is synchronized with 8th clock cycle after reset, and the first data is output.
Data held on positive edge of SI LATCH after the data transfer by single device (after 8 clock cycles)
Indicates undefined logic state after reset and before input.
Serial data transfer timing (standard current adjustment, SI SEL = H, two devices connected in cascade)
RESET
SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L
Indicates undefined logic state after reset and before input. SODATA is synchronized with 8th clock cycle after reset, and the first data is output.
Data held on positive edge of SI LATCH after the data transfer by two devices (after 16 clock cycles)
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Serial data transfer: dot adjustment DAC4. (data register SI REG2 [127:0])
Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function
1 H or L 2 (x128)
L
L
H or L
Selects dot adjustment (128 bits) for input data. Data is transferred to SI REG2 on 128th positive edge of SI CLK. Holds the data transferred to SI REG2 on positive edge of SILATCH. Set is reflected on dot adjustment from the moment when it is held.
L (x1)
L
No change
Serial data transfer timing (dot adjustment, SI SEL = L, single device)
RESET
SI SEL SI DATA SI CLK
There pairs of bits are Don't care.
Dot adjustment data for OUT 15 (1st device). SI LATCH SO DATA (1st device)
Dot adjustment data for OUT 00 (1st device).
Data held on positive edge of SI LATCH after data transfer by single device (after 128 clock cycles)
Data reset by RESET = L
Indicates undefined logic state after reset and before input.
SODATA is synchronized with 128th clock cycle after reset, and the first data is output.
Serial data transfer timing (dot adjustment, SI SEL = L, two devices connected in cascade)
RESET
SI SEL SI DATA SI CLK
There pairs of bits are Don't care.
Dot adjustment data for OUT 15 (1st device). SI LATCH SO DATA (1st device)
Dot adjustment data for OUT 00 (1st device).
Dot adjustment data for OUT 15 (2nd device).
Dot adjustment data for OUT 00 (2nd device).
Data reset by RESET = L
Indicates undefined logic state after reset and before input.
SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Data held on positive edge of SI LATCH after data transfer by two devices (after 256 clock cycles)
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DAC1: Standard current adjustment settings for DAC1 (SI REG1 [7:6])
RESET
SI SEL H H H H
SI REG (7:6) HH HL LH LL
SI REG (5:0) XXXXXX XXXXXX XXXXXX XXXXXX
Current Rate 100% (1.0) 75% (0.75) 50% (0.5) 25% (0.25) 25% (0.25)
Operation and Function
Notes
H H H H
X
LL
LLLLLL
100% of base current setting as determined by REXT () When SI SEL = H, 2 bits on 75% of base current setting as determined by REXT MSB sides are () corresponding to set of standard 50% of base current setting as determined by REXT current () adjustment 25% of base current setting as determined by REXT DAC1. The output () current can be set to one of 4 Initial state after input of reset signal: 25% of base levels. current setting as determined by REXT () (as described above)
DAC2: Standard current adjustment settings for DAC2 (SI REG1 [5:0])
RESET
SI SEL H
SI REG (7:6) XX
SI REG (5:0) XXXXXX HHHHHL
Current Rate 100% (1.0) (0.9905)
Operation and Function 100% of base current value as set using DAC1 base current adjustment
Notes
H
H
H
XX
LLLLLH
Any one or 64 levels in the range 40%~100% of the current can be set. (1 LSB = 0.95%) 1LSB = 6-bit DAC performance 0.95% 1LSB variation: 0.95% (0.0095) Non linearity error: 1/2LSB Differential non linearity error: 3/4LSB (0.4095) 40% (0.4) 40% (0.4) 40% of base current value as set using DAC1 base current adjustment Initial state after input of reset signal: 40% of base current value set as described above
H
H X
XX LL
LLLLLL LLLLLL
When SI SEL = H, 6 bits on MSB sides are corresponding to set of standard current adjustment DAC2. The output current can be set to one of 64 levels.
DAC4: Set details of dot adjustment DAC4 (SI REG2 [127:0])
RESET
SI SEL
DCEN
About 8 bits Unit of SI REG2 [127:0] XXHHHHHH
Current Rate 100% (1.0) (0.9874) 1LSB = 1.269% (0.0126) (20.0126) 20% (0.2) 20% (0.2)
Operation and Function Output current is 100% of base current value as set using DAC1 and DAC2 base current adjustment and DAC3 surface brightness adjustment Any one of 64 levels in the range 20%~100% of the current can be set. (1LSB 1.27%) - 6-bit DAC performance 1LSB variation: 1.269% Non linearity error: 1/2LSB Differential non linearity error: 1/2LSB
Notes When SI SEL = L 8 bits out of 128 bits are corresponding to set of each output, and the 6 bits on MSB sides of 8 bits are data on dot adjustment. The output current can be set to one of 64 levels.
H
L
H
XXHHHHHL H L H
XXLLLLLH
H
L
H
XXLLLLLL
X
H
XXLLLLLL
SI REG2 [7:0] adjustment data for OUT 00. SI REG2 [15:8] 20% of base current value as set using adjustment data for DAC3 surface brightness adjustment OUT 01. Initial state after input of reset signal: 20% SI REG2 [127:120] adjustment data for of base current value set as described OUT 15. above Output current is 100% of base current value set as described above. Data input is still enabled if DCEN = L. If DCEN = H, adjustment is performed at the same time.
H
X
L
XXHHHHHH
100% (1.0)
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TB62718AFG
Polarity of serial input data for standard current adjustment (SI REG1 [7:0]) and dot adjustment (SI REG2 [127:0]) Serial data transfer timing (SI SEL = H, input of standard current adjustment data for DAC1 and DAC2)
Standard current adjustment data (6 bits) SI DATA Standard current adjustment data (2 bits) SO DATA
D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F SI REG1 (7) SI REG1 (0) MSB LSB D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT
SI LATCH
Serial data transfer timing (SI SEL = L, input of dot adjustment data for DAC4)
Not used Not used
Dot adjustment data (6 bits) SI DATA SI REG2 (0) LSB SI LATCH
Dot adjustment data (6 bits)
xx SI REG2 (7)
xx
SO DATA SI REG2 (127) MSB
SI REG2 (120)
DAC4 (6-bit DAC)
DAC4 (6-bit DAC)
OUT 00
OUT 15
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TB62718AFG
Parallel data transfer: All dot adjustment DAC3. (data register PI REG1 [7:0])
Process PI DATA [7:0] PI CLK PI LATCH PI SEL PO DATA [7:0] Operation and Function Selects total dot adjustment (8-bit, 3-bit and 5-bit) for input data. Data is transferred to PI REG1 on 128th positive edge of PI CLK.
1 H or L 2 (x1)
L
H
H or L
L (x1)
H
No change
Holds the data transferred to PI REG1. Set is reflected on all dot adjustment from the moment when it is held.
Parallel data transfer timing (all dot adjustment, PI SEL = H, single device)
RESET
PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] 000_00000 111_11111 PO DATA is synchronized with 1st clock cycle after reset, and the first data is output. Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) 111_11111
Indicates undefined logic state after reset and before input.
Parallel data transfer timing (all dot adjustment, PI SEL = H, two devices connected in cascade)
RESET
PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] (1st device) 000_00000 111_11111 111_11111 110_11110 101_11101
Indicates undefined logic state after reset and before input.
Data held on positive edge of PI LATCH after the data 110_11110 transfer by two devices (2 clock cycles) PO DATA is synchronized with 2nd clock cycle after reset, and the second data is output.
PO DATA is synchronized with 1st clock cycle after reset, and the first data is output.
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Parallel data transfer PMW display data (data register PI REG2 [127:0])
Process PI DATA PI CLK PI LATCH PI SEL PO DATA Operation and Function Selects for input data of PWM display data (8 bit x 16). Data is transferred to PI REG2 on 16th positive edge of PI CLK. Holds the data transferred to PI REG2. Set is reflected on PWM 256 grayscales from the next BLANK = L when it is held.
1 H or L 2 (x16)
L
L
H or L
L (x1)
L
No change
Parallel data transfer timing (PWM data PI SEL = L, single device)
RESET
PWM data for OUT 15 PI SEL PI DATA [7:0] PI CLK 01H 02H 0EH 0FH
PWM data for OUT 00
PI LATCH PO DATA [7:0] 00H 00H 01H
Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle)
Indicates undefined logic state after reset and before input.
PO DATA is synchronized with 16th clock cycle after reset, and is output.
Parallel data transfer timing (PWM data PI SEL = L, two devices connected in cascade)
RESET
PI SEL PI DATA [7:0] PI CLK PWM data for OUT 15 (1st device) 00H 00H PWM data for OUT 00 (1st device) 01H 02H 0FH 10H 01H 00H 01H 02H 0EH 0FH 10H 01H 02H 0EH 0FH 10H
PI LATCH PO DATA [7:0] (1st device)
Indicates undefined logic state after reset and before input.
PO DATA is synchronized with 16th clock cycle after reset, and the first data is output.
Data held on positive edge of PI LATCH after data transfer by two devices (32 clock cycles)
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TB62718AFG
Details all dot adjustment setting using PWMCLK division (PI REG1 [7:5])
RESET
PI SEL H
BCEN
PI REG1 [7:5] LLL LLH
PWMCLK Divisor PWM CLK = 8/8 PWMCLK (Hz)
Operation and Function The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. Variable does the frequency of PWMCLK to 1/8 of the minimal. It is set in 8 levels. 6-bit DAC performance Maximum input: PWMCLK = 20 MHz The period of PWMCLK is set to one-eighth the change in the PWM pulse width data. 1 LSB. The period of PWMCLK is set to equal the change in the PWM pulse width data. 1 LSB. BCEN signal does not affect PWMCLK frequency dividing.
Notes
H
H
H
H
H
HHL
7/8 PWMCLK to 2/8 PWMCLK
When PI SEL = H is selected, 3 bits on MSB sides are corresponding to set of standard current adjustment by PWM frequency dividing. PI REG [7:5] varies the pulse width of PWM data corresponding to 1 LSB for eight levels and adjusts brightness. This setting values affects pulse widths on all outputs.
H
H
H
HHH
PWMCLK = 1/8 PWMCLK (Hz) PWMCLK = 8/8 PWMCLK (Hz)
X
H
LLL
H
H
L
XXX
Unchanged
Data input is still enabled if BCEN = L. Output current level reflects input settings.
DAC3: Details of all dot adjustment setting for DAC3 (PI REG2 [4:0])
RESET
PI SEL
PI REG1 [4:0] HHHHH
BCEN
Current Rate 100% (1.0) (0.9839)
Operation and Function 100% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment
Notes
H
H
H
H
H
HHHHL
LLLLH
H
Any one of 32 levels in the range 50%~100% of the current can be set. (1 LSB = 1.61%) 1LSB = 5-bit DAC performance 1.61% 1LSB variation: 1.61% (0.0161) Non linearity error: 1/2LSB Differential non linearity error: 1/2LSB (0.5161) (No guarantee for monotonicity) 50% (0.5) 50% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment Initial state after input of reset signal: 100% of base current value set as described above Initial state after input of DCEN signal: 100% of base current value set as described above
When PI SEL = H is selected, 5 bits on LSB side are corresponding to set of surface brightness adjustment. The output current can be set to one of 32 levels.
H
H
LLLLL
H
X
HHHHH
H
100% (1.0)
H
X
HHHHH
L
100% (1.0)
Data input is still enabled if BCEN = L. If BCEN = H, adjustment is performed at the same time.
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Detailed PWM 256 grayscales setting (PI REG2 [127:0], 16 x 8 bits)
RESET
PI SEL L
1 word (8 bits) of PI REG2 HHHHHHHH HHHHHHHL
Output Pulse Rate 255/255 100%
Operation and Function Output pulse width is at its maximum value when input data is FF.
Notes When PI SEL = L, The PWM grayscale controls the output pulse width.
H
H
L
LLLLLLLH
H
L
LLLLLLLL
0/255 0% 0/255 0%
16 x 8-bit words are transferred in parallel. The input data can be used to 1 word is the PWM data of each output control the PWM pulse width pulse width is set in 256 step. and hence generate 256 PI REG2 [7:0] grayscales. PWM data for OUT 00. PI REG2 [15:8] PWM data for OUT 01. Outputs are OFF when the PI REG2 [127:120] input data is 00. PWM data for OUT 15. Early condition after the reset signal input is set in 0/256 (output off). Minimum output pulse width is 1/PWMCLK.
X
LLLLLLLL
Polarity of serial input data for all dot adjustment (PI REG [7:0]) and PWM 256 grayscales (PI REG2 [127:0]) Parallel data transfer timing (PI SEL = H, selects data input for all dot adjustment for DAC3.)
PI REG1 [7] MSB PI DATA [7] All dot adjustment by division by PWMCLK PO DATA [7]
All dot adjustment by DAC3 PI DATA [0] LSB PI REG1 [0] PI LATCH PO DATA [0]
(PI SEL = L, selects data input for PWM 256 grayscales.)
PI REG2 [7] MSB PI DATA [7]
PO REG2 [127] MSB PO DATA [7]
PWM pulse data
PWM pulse data
PI DATA [0] LSB PI REG2 [0] PI LATCH PWM pulse generator circuit OUT 00 LSB PI REG2 [120]
PO DATA [0]
PWM pulse generator circuit OUT 15
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Reference table: output current setting vales (1)
DAC1 (2-bit) No. 3 2 1 0 Input Data 11 10 01 **00 Current Rate1 1.00 0.75 0.50 **0.25 No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC2 (6-bit) Input Data 111111 111110 111101 111100 111011 111010 111001 111000 110111 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 100000 011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 **000000 Current Rate2 1.000 0.990 0.981 0.971 0.962 0.952 0.943 0.933 0.924 0.914 0.905 0.895 0.886 0.876 0.867 0.857 0.848 0.838 0.829 0.819 0.820 0.800 0.791 0.781 0.771 0.762 0.752 0.743 0.733 0.724 0.714 0.705 0.695 0.686 0.676 0.667 0.657 0.648 0.638 0.629 0.619 0.610 0.600 0.591 0.581 0.571 0.562 0.552 0.543 0.533 0.524 0.514 0.505 0.495 0.486 0.476 0.467 0.457 0.448 0.438 0.429 0.419 0.410 **0.4 No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC3 (5-bit) Input Data **11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Current Rate3 **1.000 0.984 0.968 0.952 0.936 0.919 0.903 0.887 0.871 0.855 0.839 0.823 0.807 0.790 0.774 0.758 0.742 0.726 0.710 0.694 0.677 0.661 0.645 0.629 0.613 0.597 0.581 0.565 0.549 0.532 0.516 0.500 No. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC4 (6-bit) Input Data 111111 111110 111101 111100 111011 111010 111001 111000 110111 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 100000 011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 **000000 Current Rate4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note 7: **: Indicates post-reset initialization value ( RESET = L). Note 8: The formula for calculating resistance settings is as follows: This value is theory value. Actual current value contains error and so on in this value. REXT [k] = (1.9 x current rate 1 x current rate 2 x current rate 3 / output current [mA]) x (1 + (7 x current rate 4 / 105)) x 19.4
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Reference table: output current setting value (2) Reference value for standard current adjustment under conditions: REXT = 2.7 k (fixed), all dot adjustment = MSB and dot adjustment = MSB
Unit: mA DAC2 0 0 1 2 3 7.1 14.2 21.3 28.4 1 7.3 14.5 21.8 29.1 2 7.4 14.9 22.3 29.6 3 7.6 15.2 22.8 30.4 4 7.8 15.6 23.3 31.1 5 7.9 15.9 23.8 31.8 6 8.1 16.2 24.3 32.5 7 8.3 16.6 24.9 33.1 8 8.5 16.9 25.4 33.8 9 8.6 17.2 25.9 34.5 10 8.8 17.6 26.4 35.2 11 9.0 17.9 26.9 35.8 12 9.1 18.3 27.4 36.5 13 9.3 18.6 27.9 37.2 14 9.5 18.9 28.4 37.9 15 9.6 19.3 28.9 38.6
DAC1
DAC2 16 0 1 2 3 9.8 19.6 29.4 39.2 17 10.0 19.9 29.9 39.9 18 10.1 20.3 30.4 40.6 19 10.3 20.6 30.9 41.2 20 10.5 21.0 31.4 41.9 21 10.7 21.3 32.0 42.6 22 10.8 21.6 32.5 43.3 23 11.0 22.0 33.0 44.0 24 11.2 22.3 33.5 44.6 25 11.3 22.7 34.0 45.3 26 11.5 23.0 34.5 46.0 27 11.7 23.3 35.0 46.7 28 11.8 23.7 35.5 47.3 29 12.0 24.0 36.0 48.0 30 12.2 24.3 36.5 48.7 31 12.3 24.7 37.0 49.4
DAC1
DAC2 32 0 1 2 3 12.5 25.0 37.5 50.0 33 12.7 25.4 38.0 50.7 34 12.9 25.7 38.6 51.4 35 13.0 26.0 39.0 52.1 36 13.2 26.4 39.6 52.7 37 13.4 26.7 40.1 53.4 38 13.5 27.0 40.6 54.1 39 13.7 27.4 41.1 54.8 40 13.9 27.7 41.6 55.4 41 14.0 28.1 42.1 56.1 42 14.2 28.4 42.6 56.8 43 14.4 28.7 43.1 57.5 44 14.5 29.1 43.6 58.1 45 14.7 29.4 44.1 58.8 46 14.9 29.8 44.6 59.5 47 15.0 30.1 45.1 60.2
DAC1
DAC2 48 0 1 2 3 15.2 30.4 45.6 60.9 49 15.4 30.8 46.1 61.5 50 15.6 31.1 46.7 62.2 51 15.7 31.4 47.2 62.9 52 15.9 31.8 47.7 63.6 53 16.1 32.1 48.2 64.2 54 16.2 32.5 48.7 64.9 55 16.4 32.8 49.2 65.6 56 16.6 33.1 49.7 66.3 57 16.7 33.5 50.2 66.9 58 16.9 33.8 50.7 67.6 59 17.1 34.1 51.2 68.3 60 17.2 34.5 51.7 69.0 61 17.4 34.8 52.2 69.6 62 17.6 35.2 52.7 70.3 63 17.8 35.5 53.2 71.0
DAC1
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Temperature detection function (can be monitored via the ALARM1 pin.)
Perform two-stage temperature detection as described in the table below (TSD1/TSD2).
Junction Temperature [C]
-40~120
ALARM1 OFF ON
OUT 00~OUT 15 Normal operation Normal operation
Function
120~
When the chip temperature reaches the specified range the ALARM1 signal goes Low (TSD1), Other functions are not affected. When the chip temperature reaches the specified range the ALARM1 signal goes Low and all output pins are turned OFF (TSD2).
140~
ON
OFF
Outputs are re-enabled on the positive edge of TSENA or when the RESET signal goes Low. Neither of these causes the internal data to be reset. If RESET pin = L, all internal data is reset.
Output-open detection function (can be monitored via the ALARM2 pin.)
Reform output-open detection as described in the table below.
Output Voltage [V] ALARM2 OFF ON Function
> VDD x 0.04 = < VDD x 0.04 =
The output-open condition is detected when the ARARM2 pin signal is ON and the specified voltage level is detected. (it is also detected when the output voltage falls to near GND for some reason)
Pulse cancellation circuit (when monitored using output-open detection pin ARARM2.)
PWMCLK Input signal No input ALARM2 Operating Always OFF The built-in pulse cancellation circuit is designed to prevent malfunction. However, if there is no input on PWMCLK, ALARM2 output will not be turned ON. Function
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Block Diagram of Protection Circuit
RESET
Output-OFF condition is released and internal data is reset.
LED TEST
Output ON
TSENA
Release of output OFF on positive edge Constantcurrent output TSD2 TSD1 Output OFF
ALARM1
ALARM2
Pulse cancel
Output-open detection Continue one, open condition is detected. 16 OUT00~OUT15
Protection circuit function Operating chart (terminal for TESNA, ALARM1 and outputs OUT 00~OUT 15)
TSENA RESET Junction Temperature (unit: C) TSD1 TSD2 Tj < 120C 120 < Tj 140 < Tj = = = < 160C < 180C = =

ALARM1
OUT 00 ~ OUT 15 ON ON ON Normal operation
Function
X X X X
L H L H

OFF OFF ON ON
Device reset Outputs operate normally. Device reset ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. Even after a reset, if the junction temperature is high, outputs are turned OFF. ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally.

X
L
ON
OFF
X
H
ON
OFF
Note 9: The internal operation of the TSD circuit is independent of the TSENA and RESET pin voltage levels.
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Serial Data Input Timing Chart
BLANK Output OFF
RESET
Output ON
Data of DAC3 for OUT 15 SI DATA Data of DAC1 to 2 x8 x8
Data of DAC3 for OUT 00
SI CLK
x8
SI LATCH
SI SEL
Selects input of standard current adjustment data.
Selects input of each dot adjustment data.
SO DATA The data read with 1st time SO DATA outputs standard current SO DATA outputs each dot adjustment data.
The data read with 1st time
Note 10: Serial data input has no effect on the ON/OFF state of the outputs. When the SI LATCH signal holds the serial data, the output current values and output pulse width are affected.
Parallel Data Input Timing Chart
Output OFF & data hold BLANK Output ON & data transfer Output ON & data transfer
RESET
DOE PWM data for OUT 15 PI DATA 00~ PI DATA 07 for total dot adjustment PI CLK 1 Time PI LATCH Holds PWM data, output-ON data and total dot adjustment data. Selects input of total dot adjustment PI SEL PO DATA 00~ PO DATA 07 High-Impedance The data read with 1st time PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output all bit adjustment data. OUT 00~ OUT 15 PO DATA 00~PODATA 07 output PWM data. Selects input of PWM data and output-ON data. High-Impedance Selects input of PWM data and output-ON data. The data read with 1st time 16 Times PWM data for OUT 00
Output ON (output-OFF if PWM data = 0)
OFF Starts output of PWM data after synchronizing with rising edge of BLANK.
Note 11: The BLANK signal has not effect on parallel data input. The PWM pulse can be controlled using the BLANK signal. It is recommended that, on completion of data transfer, BLANK be set to High and outputs be turned OFF.
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PWM Operating Timing Chart and All Bit Adjustment Using Division by PWMCLK
Output OFF, data hold BLANK Output can be turned ON. Output OFF, data change & hold Output can be turned ON.
RESET
OUT 00~ OUT 15
ON
OFF
ON
OFF
tBLANK (8) tBLANK (7) tBLANK (6) PWMCLK division tBLANK (5) tBLANK (4) tBLANK (3) tBLANK (2) tBLANK (1) tBLANK (7) = (1/ (7/8PWMCLK) ) x 256 tBLANK (6) = (1/ (6/8PWMCLK) ) x 256
Minimum PWM control time tBLANK (8) = (1/ (8/8PWMCLK) ) x 256
tBLANK (5) = (1/ (5/8PWMCLK) ) x 256 tBLANK (4) = (1/ (4/8PWMCLK) ) x 256 tBLANK (3) = (1/ (3/8PWMCLK) ) x 256 tBLANK (2) = (1/ (2/8PWMCLK) ) x 256 Maximum PWM control time tBLANK (1) = (1/ (1/8PWMCLK) ) x 256
OUT 00~OUT 15 PWM data = 00 H OUT 00~OUT 15 PWM data = 01 H PWMCLK8 OUT 00~OUT 15 PWM data = 80 H PWMCLK8 OUT 00~OUT 15 PWM data = FE H PWMCLK8
Output OFF because data is 00H though it can on.
Because data is 01 H output is ON with 1/255 of tBLANK.
Because data is 80 H output is ON with 128/255 of tBLANK. Because data is 80 H output is ON with 254/255 of tBLANK.
Note 12: PWM operation timing: PWM pulse output on the output pins is initiated when BLANK goes Low. (there is simultaneous output on all 16 pins) Output pulse only once toward BLANK signal's changing once in L from H. Hence, if PWM data is to be re-used, BLANK must be pulled Low again. PWMCLK division: As shown in the central part of the upper figure, the brightness of the LED module can be set to any one of eight levels without adjusting the current value, simply by dividing by PWMCLK. For large-scale brightness adjustment, division by PWMCLK is recommended.
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Logic Input and Output Timing Waveforms
1. PI CLK (SI CLK) vs. PI DATA [7:0] (SI DATA) PI CLK (SI CLK) vs. PO DATA [7:0] (SO DATA)
twH PI CLK (SI CLK) twL
50%
50%
50%
PI DATA [7:0] (SI DATA)
50%
50%
tsetup PO DATA [7:0] (SO DATA)
thold
50%
50%
tpd
tpd
2. PI SEL (SI SEL) vs. PI CLK (SI CLK)
twH PI CLK (SI CLK) twL
50%
50%
50%
PI DATA [7:0] (SI DATA)
PI SEL (SI SEL) tsetup thold
50%
50%
50%
tsetup
thold
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3. PI LATCH (SI LATCH) vs. PI CLK (SI CLK)
twH PI CLK (SI CLK) twL
50%
50%
50%
PI DATA [7:0] (SI DATA)
(Internal flip-flop data) tsetup PI LATCH (SI LATCH) 50% thold 50% 50%
twltH
twltL
4. PI SEL (SI SEL) vs. PO DATA 00~PO DATA 07 (SO DATA)
PI SEL (SI SEL)
50%
50%
PO DATA [7:0] (SO DATA) tpd
50%
50%
tpd
5. DOE vs. PO DATA 00~PO DATA 07
DOE
50%
50%
PO DATA [7:0]
tpzH/zL
tpzH/zL
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Logic Input and Constant-current Output Timing Waveforms
1. BLANK vs. OUT 00~OUT 15 with PWMCLK
twblkL twblkH
BLANK
50%
50%
50%
50%
PWMCLK
Maximum delay time is 1 PWMCLK cycle. OUT 00~OUT 15 (current waveform)
Maximum delay time is 1 PMCLK cycle.
50%
50%
tpLH
tpHL
2. RESET vs. OUT 00~OUT 15
BLANK twrstL
RESET
50%
50%
OUT [15:0] (current waveform) tpHL
50%
3. LED TEST vs. OUT 00~OUT 15
twledH
LED TEST
50% tpLH
50%
OUT 00~OUT 15 (current waveform)
50% tpHL
50%
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Package Dimensions
Weight: 0.26 g (typ.)
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About solderability, following conditions were confirmed * Solderability Use of Sn-63Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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